A tunneling effect transistor is essentially a gated tunnel diode. The tunneling effect transistor is of interest for future semiconductor systems because of its steep subthreshold voltage slope. Thus, the ratio of on-current to off-current may be higher than conventional field effect transistors in low voltage operations, for example, at or below 1.0V.
While demonstrating such favorable device characteristics, currently known tunneling effect transistors are not suitable for integration into practical products due to low drive current per unit area compared with conventional field effect transistors. In general, prior art tunneling effect transistors do not provide self-alignment, which results in a large footprint on a substrate area. Further, the large footprint is unavoidably associated with a large parasitic capacitance, further degrading device performance as an electronic switch.
U.S. Pat. No. 6,617,643 to Goodwin-Johansson discloses a three-terminal tunneling device. In addition to requiring epitaxy of a silicon layer that adds to processing complexity, this prior art structure discloses a p+ doped region on one side of a gate and an n+ doped region on the other side of the gate. This requires a gate length greater than the overlay tolerance of block masks that are employed during masked ion implantation steps. Thus, the gate cannot have a sublithographic length, which becomes a limiting factor in scaling this prior art device. Further, reduction of input capacitance of this prior art device is necessarily limited by the relatively large physical size.
Song et al., “Analytical Modeling of Field-Induced Interband Tunneling-Effect Transistors and Its Application,” IEEE Transactions on Nanotechnology, Vol. 5, No. 3, May 2006, pp. 192-200 discloses a variant of a conventional field effect transistor having a heavily doped channel that produces interband tunneling during operation. The gate is formed by conventional lithographic means, and consequently, has a lithographic length. Thus, the size of this device is about the same as conventional field effect transistors.
Zhang et al., “Design and Modeling of a New Silicon-Based Tunneling Field Effect Transistor,” IEEE Transactions on Electron Devices, Vol. 43, No. 9, September 1996, pp. 1441-1447 discloses a vertical tunneling field effect transistor. However, this prior art structure requires many epitaxial silicon deposition steps, which is difficult to incorporate into standard complementary metal oxide semiconductor (CMOS) processing steps.
Bhuwalka et al., “Scaling the Vertical Tunnel FET with Tunnel Bandgap Modulation and Gate Workfunction Engineering,” IEEE Transactions on Electron Devices, Vol. 52, No. 5, May 2005, discloses a vertical tunneling transistor structure having many heterojunctions. Manufacturing of this structure requires many epitaxial silicon deposition steps, which may not be easily integrated into standard CMOS processing sequences.
In view of the above, there exists a need for a self-aligned tunneling effect transistor having a small footprint and small parasitic capacitance, and methods of manufacturing the same.
Further, there exists a need for a self-aligned tunneling effect transistor having a sublithographic gate length, and methods of manufacturing the same.
In addition, there exists a need for a self-aligned tunneling effect transistor that may be manufactured by processing steps that are easily integrated into a standard CMOS processing sequence.